Implementing and Optimizing a Direct Digital Frequency Synthesizer (DDFS) on FPGA
نویسندگان
چکیده
منابع مشابه
Design and Simulation of a Modified 32-bit ROM-based Direct Digital Frequency Synthesizer on FPGA
This paper presents a modified 32-bit ROM-based Direct Digital Frequency Synthesizer (DDFS). Maximum output frequency of the DDFS is limited by the structure of the accumulator used in the DDFS architecture. The hierarchical pipeline accumulator (HPA) presented in this paper has less propagation delay time rather than the conventional structures. Therefore, it results in both higher maximum ope...
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